Printing Copper Multilayers with VIAs on 3D Surfaces using Laser Material Processing
Zusammenfassung
This thesis investigates how laser-assisted printing of multilayer copper conductive traces and vertical interconnect accesses (VIAs) enhances the miniaturization of 3D mechatronic integrated devices (MIDs). The primary objective is to improve the integration of 3D circuit carriers and address current miniaturization challenges. The state-of-the-art analysis includes a novel classification for 3D multilayer devices (MLDs) and an evaluation of different VIA printing approaches. Experimental results include the parameterization of laser sintering, cleaning, and ablation processes. Further topics are the process adaptation to 3D surfaces and the optimization of copper VIA printing. Prototypical 3D MLD circuits demonstrate enhanced design flexibility for 3D multilayer resonators, lighting devices, and high-density contact pads, achieving a 100% working ratio for conductive VIAs under optimal coating conditions and low mean VIA resistances below one ohm.
Schlagworte
- Kapitel Ausklappen | EinklappenSeiten
- I–XVI Titelei/Inhaltsverzeichnis I–XVI
- 1–4 1. Introduction 1–4
- 5–44 2. State of the Art 5–44
- 2.1. 3D Structural Electronics
- 2.2. Printed Electronics
- 2.3. Laser Material Processing
- 2.4. Conclusion
- 45–50 3. Task Assignment 45–50
- 3.1. Multilayer Printing Approach
- 3.2. Sub-goals Specification
- 3.3. Sub-goals Structure
- 51–60 4. Setup and Methodology for Laser Processing of Printed Electronics 51–60
- 4.1. Laser Systems
- 4.2. Copper and Insulator Inks
- 4.3. Sample Preparation
- 61–78 5. Laser Processing Parametrizationon Planar Substrates 61–78
- 5.1. Laser Sintering of Copper Ink
- 5.2. Laser Cleaning of Copper Ink
- 5.3. Laser Ablation of Insulator Ink
- 5.4. Laser System Assessment
- 79–84 6. Single Layer Electronic Circuit Printing on 3D Spatial Surfaces 79–84
- 6.1. 3D Surface Priming with Insulator Ink
- 6.2. 3D Laser Sintering of Copper Ink
- 6.3. 3D Laser Cleaning of Residual Ink
- 6.4. 3D Single-Layer Demonstrators
- 85–98 7. Copper VIA Printing 85–98
- 7.1. Resistance Model
- 7.2. Double-Layer VIA Test Design
- 7.3. Process Optimization
- 7.4. Conclusion
- 99–114 8. Multilayer Device Demonstrators 99–114
- 8.1. 3D Double-Layer Resonator Circuit
- 8.2. 3D Double-Layer LED Circuit
- 8.3. 3D Double-Layer Multidirectional Lighting Circuit
- 8.4. 2D Five-Layer Contact Pad Array
- 115–116 9. Conclusion 115–116
- 117–118 10. Outlook 117–118
- 119–140 Appendix 119–140
- A. Mechatronic Integrated Device Geometry Classification Schematics
- B. Multilayer Device Geometry and Technology Nomenclature
- C. Technical Data of Laser Marking Systems
- D. Material Data of the Functional Inks and Pastes
- E. Sintering Parametrization Resistance Measurements
- F. Cleaning Parametrization Depth Measurements
- G. Ablation Parametrization Depth and Width Measurements
- H. Process Development Resistance Measurements
- I. 3D Double-Layer Multidirectional Lighting Circuit
- 141–143 List of Figures 141–143
- 144–145 List of Tables 144–145
- 146–164 Bibliography 146–164
- 165–175 Relevant Publications 165–175
